As IC complexity increases, designers rely largely on simulation and analysis to verify and qualify IC designs. Accurate behavioral IC models are crucial for accurate simulation and analysis. With IC densities increasing such that line-widths are much less than one micron, random fluctuations in the manufacturing process introduce process variations in the fabrication of ICs. Process variations can be typically broken up into two levels: inter-die variations and intra-die variations. The inter-die variations can be modeled to address common variations across the die, while the intra-die variations can be modeled to address individual, but spatially correlated, local variations within the die. Both inter-die and intra-die process variations can significantly impact circuit performance, production yields, or both. Meanwhile, metal interconnects of integrated circuits are exerting greater influences on IC behavior; therefore, accurate interconnect models are needed. Variations in process parameters that influence interconnect behavior need to be included in the interconnect models. The process parameters may include width and thickness of the metal interconnects. Interconnect models including variational process parameters are called parameterized interconnect models. In large ICs, the number of interconnects can number in the hundreds of millions resulting in very large interconnect models for large ICs. Thus, there is a need to simplify and reduce the size of IC interconnect models, while retaining as much behavioral accuracy as possible. Such models are called reduced-order IC interconnect models and may be represented using matrix based vector equations.
The matrices of a parameterized reduced-order IC interconnect model with consideration of inter-die process variations only can be approximated as low-order polynomials of the process parameters; however, the matrices of a parameterized reduced-order IC interconnect model may be strongly non-linear in the presence of intra-die process variations. Therefore, using low-order polynomials of the process parameters for intra-die variations may not be feasible. Thus, there is a further need for a parameterized reduced-order IC interconnect model, which incorporates variations in interconnect process parameters including both inter-die and intra-die variations.